1. Field of the Invention
The present invention relates to a semiconductor device of high withstand voltage having an offset drain and a method of producing the same, more particularly a MOS transistor of a high withstand voltage realizing both an improvement in the junction breakdown voltage and a decrease in on-resistance and a method of producing the same.
2. Description of the Related Art
In recent years, along with the spread of personal computers and the increase in size of televisions for home use, the market for displays has expanded rapidly. In the current market for displays, cathode ray tubes (CRTs) having a high definition, a high luminance, a wide viewing angle, and a high contrast are the most widespread. However, when a cathode ray tube is enlarged, the problem of an increase in the space occupied and the weight arises. Therefore, expectations have been rising for liquid crystal displays, plasma displays, and other flat panel displays capable of being made thinner and lighter as the next-generation displays.
In these flat panel displays, in the process of production of the electric field driving board controlling the intensity of the electric field for a pixel cell, it is necessary to form an electric field driving circuit having a high withstand voltage of several hundred V on a semiconductor substrate for controlling the plasma.
FIGS. 8A and 8B are cross-sectional views illustrating fundamental structures of conventional MOS transistors of high withstand voltages. The MOS transistors of high withstand voltages shown in FIG. 8 are called LOD (LOCOS offset drain)-type MOS transistors.
In an LOD-type MOS transistor, an n+-type drain region 25 is formed away from a p-well 7 by a LOCOS oxide layer 11 for the purpose of securing a high junction breakdown voltage (BVds). On the other hand, an n+-type source region 24 and a p+-type p-well plug region (a p+-type source region) 23 are short-circuited with a source electrode 27, thus a depletion layer extends from a junction of the p-well 7 and an n-type drift region 29 to the n-type drift region 29 when a reverse bias is supplied between the source and the drain. The withstand voltage of the transistor is secured by using the extension of the depletion layer to the n-type drift region 29 for preventing concentration of the electric field (easing the electric field).
In addition, in the transistor shown in FIG. 8, it is also intended to increase the withstand voltage by a RESURF (REduced SURface Field) technique, that is, easing of the electric field using an extension of a depletion layer at the junction of a p-type substrate 1 and an n-type epitaxial layer 4 in the surface direction.
Since a RESURF structure can be easily combined with pn junction separation and the withstand voltage can be controlled by adjusting the drift region length, this is advantageous as a structure of a transistor of a high withstand voltage.
In the above structure of conventional MOS transistors of high withstand voltages, the concentration of the impurity in the n-type drift region 29 is suppressed to a low level in order to gain the RESURF effect. By lowering the concentration of the impurity in the n-type drift region 29, it is intended that the depletion layer at the junction of the p-type substrate 1 and an n-type epitaxial layer 4 cause complete depletion of the n-type drift region 29.
However, in actually, when the depletion layer at the junction of the p-type substrate 1 and the n-type epitaxial layer 4 reaches the n+-type drain region 25 containing an impurity in a high concentration, the extension of the depletion layer is prevented. Therefore, it was not possible to cause complete depletion to the surface of the n+-type drift region 29 and it was difficult to improve the junction breakdown voltage.
Further, if the concentration of the impurity in the n-type drift region 29 is lowered, the depletion layer extending from the junction of the p-well 7 and the n-type drift region 29 to the n-type drift region 29 easily reaches the edge of the n+-type drain region 25. If the depletion layer extending from the junction of the p-well 7 and the n-type drift region 29 to the n-type drift region 29 reaches the edge of the n+-type drain region 25 with a lower voltage than the withstand voltage targeted for a MOS transistor, the extension of the depletion layer is stopped. Therefore, it becomes impossible to ease the electric field and the desired withstand voltage cannot be obtained.
To avoid this, it is necessary to increase the distance between the p-well 7 and the n+-type drain region 25, that is, the drift region length shown in FIG. 8A as L. By increasing the drift region length L, it is possible to prevent the depletion region extending from the junction of the p-well 7 and the n-type drift region 29 to the n-type drift region 29 from reaching the edge of the n+-type drain region 25.
On the other hand, when the drift region length L is increased, the problem of an increase of the resistance at the instant a transistor starts operating (on-resistance; Ron) also arises.
For example, in the case of a substrate with an n-type epitaxial layer 4 having a resistivity of 5 xcexa9xc2x7cm and a thickness of 5 xcexcm and a p-type substrate having a resistivity of 10 xcexa9xc2x7cm, the drift region length L must be about 15 to 20 xcexcm in order to set the breakdown voltage between the source and the drain (BVds) at 100 V. For further raising the breakdown voltage of the MOS transistor, a greater drift region length is required. If the drift region length L is increased, the cell size and the on-resistance (Ron) proportionally increase and obstruct the increase in integration degree and speed of the semiconductor device.
As shown in FIG. 8B, there is also a MOS transistor of a high withstand voltage reduced in the resistivity of the n+-type drift region 29 by forming an n-type impurity diffusion layer 30 in the n+-type drift region 29 for the purpose of decreasing the on-resistance (Ron) of the transistor. In the case of this structure, not only does the junction breakdown voltage between the p-well 7 and the n-type drift region 29 decrease, but also complete depletion of the surface of the n-type drift region 29 is made more difficult than the case of FIG. 8A. Therefore, the junction breakdown voltage (BVds) decreases.
As mentioned above, it has been difficult to achieve both an increase in the withstand voltage of a transistor and a decrease in the on-resistance.
The present invention was made in consideration of the above problems. Therefore, the present invention has as its object to provide a semiconductor device, that is, transistor, of a high withstand voltage having a LOCOS offset drain, which can cause complete depletion of the drift region and achieve both of an improvement in the junction breakdown voltage and a decrease in the on-resistance and a method of producing the same.
To achieve the above object, the semiconductor device of the present invention provides a semiconductor device comprising; a first conductivity type semiconductor substrate; a second conductivity type semiconductor layer formed on the first conductivity type semiconductor substrate; a first conductivity type impurity diffusion layer formed in a surface region of the second conductivity type semiconductor layer; a second conductivity type source region formed in a surface region of the first conductivity type impurity diffusion layer; a second conductivity type drain region formed in the surface region of the second conductivity type semiconductor layer at a predetermined distance from the first conductivity type impurity diffusion layer; an element isolating insulation layer formed between the second conductivity type source region and the second conductivity type drain region; a gate insulating film formed between the second conductivity type source region and the second conductivity type drain region; and a gate electrode formed on the gate insulating film, wherein a buried layer containing an impurity of the first conductivity type in a higher concentration than that of the first conductivity type semiconductor substrate is formed at least in part in the surface layer of the first conductivity type semiconductor substrate except just below the second conductivity type drain region.
The semiconductor device of the present invention is preferably characterized in that the buried layer is formed in a pattern surrounding the second conductivity type drain region except just below the second conductivity type drain region.
The semiconductor device of the present invention is preferably characterized in that a second conductivity type impurity diffusion layer is formed via a junction with the first conductivity type impurity diffusion layer in the surface layer of the second conductivity type semiconductor layer; and the second conductivity type drain region is formed in the surface layer of the second conductivity type impurity diffusion layer at a predetermined distance from the first conductivity type impurity diffusion layer.
The semiconductor device of the present invention is preferably characterized in that the gate electrode is composed of polycrystalline silicon.
The semiconductor device of the present invention is preferably characterized in that the first conductivity type is a p-type while the second conductivity type is an n-type.
The semiconductor device of the present invention is preferably characterized in that the second conductivity type semiconductor layer is an epitaxial layer.
The semiconductor device of the present invention is preferably characterized in that the gate insulating film is a silicon oxide film.
Further, to achieve the above object, the method of producing a semiconductor device of the present invention comprises the steps of: introducing a first conductivity type impurity into a surface layer of a first conductivity type semiconductor substrate to form a first conductivity type buried layer containing an impurity in a higher concentration than that of the first conductivity type semiconductor substrate; growing epitaxially a second conductivity type semiconductor layer on the first conductivity type semiconductor substrate; forming a first conductivity type impurity diffusion layer connected to the first conductivity type buried layer in the surface layer of the second conductivity type semiconductor layer; forming an element isolating insulation layer partly in the second conductivity type semiconductor layer; forming a second conductivity type source region in the surface layer of the first conductivity type impurity diffusion layer; forming a second conductivity type drain region in the surface layer of the second conductivity type semiconductor layer outside a region beneath which the first conductivity type buried layer is formed; forming a gate insulating film between the second conductivity type source region and the second conductivity type drain region and forming a gate electrode on the gate insulating film; and forming a source electrode and a drain electrode connected to the source region or the drain region respectively.
The method of producing a semiconductor device of the present invention is preferably characterized in that a step of forming a second conductivity type impurity diffusion layer comprises the second conductivity type drain region in the surface layer of the second conductivity semiconductor layer.
The method of producing a semiconductor device of the present invention is preferably characterized in that the gate electrode is composed of polycrystalline silicon.
The method of producing a semiconductor device of the present invention is preferably characterized in that the first conductivity type is a p-type while the second conductivity type is an n-type.
The method of producing a semiconductor device of the present invention is preferably characterized in that the gate insulating film is a silicon oxide film.
The method of producing a semiconductor device of the present invention is preferably characterized in that the element isolating insulation layer is formed between the second conductivity type source region and the second conductivity type drain region.